PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical

Description

CPUID

Opcode/

Op/

64/32 bit

Feature

Instruction

En

Mode

Flag

Support

0F D1 /r1

RM

V/V

MMX

Shift words in mm right by amount specified in mm/m64 while shifting in 0s.

PSRLW mm, mm/m64

66 0F D1 /r

RM

V/V

SSE2

Shift words in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.

PSRLW xmm1, xmm2/m128

MI

V/V

MMX

Shift words in mm right by imm8 while shifting

0F 71 /2 ib1

in 0s.

PSRLW mm, imm8

66 0F 71 /2 ib

MI

V/V

SSE2

Shift words in xmm1 right by imm8 while shifting in 0s.

PSRLW xmm1, imm8

RM

V/V

MMX

Shift doublewords in mm right by amount

0F D2 /r1

specified in mm/m64 while shifting in 0s.

PSRLD mm, mm/m64

66 0F D2 /r

RM

V/V

SSE2

Shift doublewords in xmm1 right by amount specified in xmm2 /m128 while shifting in 0s.

PSRLD xmm1, xmm2/m128

0F 72 /2 ib1

MI

V/V

MMX

Shift doublewords in mm right by imm8 while shifting in 0s.

PSRLD mm, imm8

66 0F 72 /2 ib

MI

V/V

SSE2

Shift doublewords in xmm1 right by imm8 while shifting in 0s.

PSRLD xmm1, imm8

RM

V/V

MMX

Shift mm right by amount specified in

0F D3 /r1

mm/m64 while shifting in 0s.

PSRLQ mm, mm/m64

66 0F D3 /r

RM

V/V

SSE2

Shift quadwords in xmm1 right by amount specified in xmm2/m128 while shifting in 0s.

PSRLQ xmm1, xmm2/m128

MI

V/V

MMX

Shift mm right by imm8 while shifting in 0s.

0F 73 /2 ib1

PSRLQ mm, imm8

66 0F 73 /2 ib

MI

V/V

SSE2

Shift quadwords in xmm1 right by imm8 while shifting in 0s.

PSRLQ xmm1, imm8

VEX.NDS.128.66.0F.WIG D1 /r

RVM

V/V

AVX

Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in 0s.

VPSRLW xmm1, xmm2, xmm3/m128

VEX.NDD.128.66.0F.WIG 71 /2 ib

VMI

V/V

AVX

Shift words in xmm2 right by imm8 while shifting in 0s.

VPSRLW xmm1, xmm2, imm8

VEX.NDS.128.66.0F.WIG D2 /r

RVM

V/V

AVX

Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in 0s.

VPSRLD xmm1, xmm2, xmm3/m128

VEX.NDD.128.66.0F.WIG 72 /2 ib

VMI

V/V

AVX

Shift doublewords in xmm2 right by imm8 while shifting in 0s.

VPSRLD xmm1, xmm2, imm8

VEX.NDS.128.66.0F.WIG D3 /r

RVM

V/V

AVX

Shift quadwords in xmm2 right by amount specified in xmm3/m128 while shifting in 0s.

VPSRLQ xmm1, xmm2, xmm3/m128

VEX.NDD.128.66.0F.WIG 73 /2 ib

VMI

V/V

AVX

Shift quadwords in xmm2 right by imm8 while shifting in 0s.

VPSRLQ xmm1, xmm2, imm8

VEX.NDS.256.66.0F.WIG D1 /r

RVM

V/V

AVX2

Shift words in ymm2 right by amount specified in xmm3/m128 while shifting in 0s.

VPSRLW ymm1, ymm2, xmm3/m128

VEX.NDD.256.66.0F.WIG 71 /2 ib

VMI

V/V

AVX2

Shift words in ymm2 right by imm8 while shifting in 0s.

VPSRLW ymm1, ymm2, imm8

VEX.NDS.256.66.0F.WIG D2 /r

RVM

V/V

AVX2

Shift doublewords in ymm2 right by amount specified in xmm3/m128 while shifting in 0s.

VPSRLD ymm1, ymm2, xmm3/m128

VEX.NDD.256.66.0F.WIG 72 /2 ib

VMI

V/V

AVX2

Shift doublewords in ymm2 right by imm8 while shifting in 0s.

VPSRLD ymm1, ymm2, imm8

VEX.NDS.256.66.0F.WIG D3 /r

RVM

V/V

AVX2

Shift quadwords in ymm2 right by amount specified in xmm3/m128 while shifting in 0s.

VPSRLQ ymm1, ymm2, xmm3/m128

VEX.NDD.256.66.0F.WIG 73 /2 ib

VMI

V/V

AVX2

Shift quadwords in ymm2 right by imm8 while shifting in 0s.

VPSRLQ ymm1, ymm2, imm8

NOTES:

1. See note in Section 2.4, “Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En Operand 1 Operand 2 Operand 3 Operand 4
RM ModRM:reg (r, w) ModRM:r/m (r) NA NA
MI ModRM:r/m (r, w) imm8 NA NA
RVM ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
VMI VEX.vvvv (w) ModRM:r/m (r) imm8 NA

Description

Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s. Figure 4-15 gives an example of shifting words in a 64-bit operand.

Note that only the first 64-bits of a 128-bit count operand are checked to compute the count.

Pre-Shift DEST Shift Right with Zero Extension Post-Shift DEST X3 X2 X0 X2 >> COUNT X1 >> COUNT X0 >> COUNT X3 >> COUNT X1

Figure 4-15. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand

The (V)PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits specified in the count operand; the (V)PSRLD instruction shifts each of the doublewords in the destination operand; and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The destination operand is an MMX technology register; the count operand can be either an MMX technology register or an 64-bit memory location.

128-bit Legacy SSE version: The destination operand is an XMM register; the count operand can be either an XMM register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits

are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be either an YMM register or a 128-bit memory location or an 8-bit immediate.

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2), VEX.vvvv encodes the destination register, and VEX.B + ModRM.r/m encodes the source register. VEX.L must be 0, otherwise instructions will #UD.

Operation

PSRLW (with 64-bit operand)

    IF (COUNT > 15)
    THEN
         DEST[64:0] ← 0000000000000000H
    ELSE
         DEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT);
         (* Repeat shift operation for 2nd and 3rd words *)
         DEST[63:48] ← ZeroExtend(DEST[63:48] >> COUNT);
    FI;

PSRLD (with 64-bit operand)

    IF (COUNT > 31)
    THEN
         DEST[64:0] ← 0000000000000000H
    ELSE
         DEST[31:0] ← ZeroExtend(DEST[31:0] >> COUNT);
         DEST[63:32] ← ZeroExtend(DEST[63:32] >> COUNT);
    FI;

PSRLQ (with 64-bit operand)

    IF (COUNT > 63)
    THEN
         DEST[64:0] ← 0000000000000000H
    ELSE
         DEST ← ZeroExtend(DEST >> COUNT);
    FI;

PSRLW (with 128-bit operand)

    COUNT ← COUNT_SOURCE[63:0];
    IF (COUNT > 15)
    THEN
         DEST[128:0] ← 00000000000000000000000000000000H
    ELSE
         DEST[15:0]  ← ZeroExtend(DEST[15:0] >> COUNT);
         (* Repeat shift operation for 2nd through 7th words *)
         DEST[127:112] ← ZeroExtend(DEST[127:112] >> COUNT);
    FI;

PSRLD (with 128-bit operand)

    COUNT ← COUNT_SOURCE[63:0];
    IF (COUNT > 31)
    THEN
         DEST[128:0] ← 00000000000000000000000000000000H
    ELSE
         DEST[31:0]  ← ZeroExtend(DEST[31:0] >> COUNT);
         (* Repeat shift operation for 2nd and 3rd doublewords *)
         DEST[127:96] ← ZeroExtend(DEST[127:96] >> COUNT);
    FI;

PSRLQ (with 128-bit operand)

    COUNT ← COUNT_SOURCE[63:0];
    IF (COUNT > 15)
    THEN
         DEST[128:0] ← 00000000000000000000000000000000H
    ELSE
         DEST[63:0]  ← ZeroExtend(DEST[63:0] >> COUNT);
         DEST[127:64] ← ZeroExtend(DEST[127:64] >> COUNT);
    FI;

PSRLW (xmm, xmm, xmm/m128)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)

PSRLW (xmm, imm8)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)

VPSRLW (xmm, xmm, xmm/m128)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0

VPSRLW (xmm, imm8)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0

PSRLD (xmm, xmm, xmm/m128)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)

PSRLD (xmm, imm8)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)

VPSRLD (xmm, xmm, xmm/m128)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0

VPSRLD (xmm, imm8)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0

PSRLQ (xmm, xmm, xmm/m128)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)

PSRLQ (xmm, imm8)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)

VPSRLQ (xmm, xmm, xmm/m128)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] ← 0

VPSRLQ (xmm, imm8)

DEST[127:0] ← LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8)
DEST[VLMAX-1:128] ← 0

VPSRLW (ymm, ymm, xmm/m128)

DEST[255:0] ← LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)

VPSRLW (ymm, imm8)

DEST[255:0] ← LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)

VPSRLD (ymm, ymm, xmm/m128)

DEST[255:0] ← LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)

VPSRLD (ymm, imm8)

DEST[255:0] ← LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)

VPSRLQ (ymm, ymm, xmm/m128)

DEST[255:0] ← LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)

VPSRLQ (ymm, imm8)

DEST[255:0] ← LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)

Intel C/C++ Compiler Intrinsic Equivalents

PSRLW:

__m64 _mm_srli_pi16(__m64 m, int count)

PSRLW:

__m64 _mm_srl_pi16 (__m64 m, __m64 count)

(V)PSRLW:

__m128i _mm_srli_epi16 (__m128i m, int count)

(V)PSRLW:

__m128i _mm_srl_epi16 (__m128i m, __m128i count)

VPSRLW:

__m256i _mm256_srli_epi16 (__m256i m, int count)

VPSRLW:

__m256i _mm256_srl_epi16 (__m256i m, __m128i count)

PSRLD:

__m64 _mm_srli_pi32 (__m64 m, int count)

PSRLD:

__m64 _mm_srl_pi32 (__m64 m, __m64 count)

(V)PSRLD:

__m128i _mm_srli_epi32 (__m128i m, int count)

(V)PSRLD:

__m128i _mm_srl_epi32 (__m128i m, __m128i count)

VPSRLD:

__m256i _mm256_srli_epi32 (__m256i m, int count)

VPSRLD:

__m256i _mm256_srl_epi32 (__m256i m, __m128i count)

PSRLQ:

__m64 _mm_srli_si64 (__m64 m, int count)

PSRLQ:

__m64 _mm_srl_si64 (__m64 m, __m64 count)

(V)PSRLQ:

__m128i _mm_srli_epi64 (__m128i m, int count)

(V)PSRLQ:

__m128i _mm_srl_epi64 (__m128i m, __m128i count)

VPSRLQ:

__m256i _mm256_srli_epi64 (__m256i m, int count)

VPSRLQ:

__m256i _mm256_srl_epi64 (__m256i m, __m128i count)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

See Exceptions Type 4 and 7 for non-VEX-encoded instructions; additionally

#UD If VEX.L = 1.