SHR              Shift Logical Right                 Flags: O D I T S Z A P C
                                                            *       * * ? * *
SHR destination,count

                           +-------------+   +----+
                      0 --.| Destination |--.| CF |
                           +-------------+   +----+

    SAR shifts the bits in destination to the right by the number of
    positions specified in the count operand (or in CL, if no count
    operand is included). 0s are shifted in on the left. If the sign bit
    retains its original value, the Overflow Flag is cleared; it is set if
    the sign changes. The Carry Flag is updated to reflect the last bit
    shifted.

    If COUNT is not equal to 1, the Overflow flag is undefined, otherwise
    the Overflow Flag is set to the high-order bit of the original
    operand.

  --------------------------------------------------------------------------
   Operands                  Clocks   Transfers  Bytes   Example
   register, 1                 2          -        2     SHR SI,1
   register, CL            8 + 4/bit      -        2     SHR SI,CL
   memory, 1                15 + EA       2       2-4    SHR ID_BYTE[SI][BX],1
   memory, CL           20 + EA + 4/bit   2       2-4    SHR INPUT_WORD,CL
  --------------------------------------------------------------------------

       Notes:         COUNT is normally taken as the value in CL. If,
                      however, you wish to shift only one position,
                      replace the second operand, CL, with the value 1, as
                      shown in the first example below.

                      The 80286 and 80386 microprocessors limit the COUNT
                      value to 31.  If the COUNT is greater than 31, these
                      microprocessors use COUNT MOD 32 to produce a new
                      COUNT between 0 and 31.  This upper bound exists to
                      limit the amount of time an interrupt response will
                      be delayed waiting for the instruction to complete.

                      Multiple SHRs that use 1 as the COUNT may be faster
                      and require less memory than a single SHR that uses
                      CL for COUNT.

                      The overflow flag is undefined when the shift count
                      is greater than 1.